Program

Workshop Program, November 16

8:45 - 9:00: Opening (with AWASE workshop)

9:00 - 9:45: AWASE keynote (Jifeng He)

9:45 - 10:00: Break

10:00 - 10:50: Session 1: Timing analysis (chair: Cyrille Artho)

• Qurat Ul Ain and Osman Hasan:
  Formal Timing Analysis of Digital Circuits
• Étienne André:
  A benchmarks library for parametric timed model checking

10:50 - 11:05: Break

11:05 - 12:20: Session 2: Decision, planning, optimization (chair: Cesar Munoz)

• Liana Mikaelyan, Sascha Müller, Andreas Gerndt and Thomas Noll:
  Synthesizing and Optimizing FDIR Recovery Strategies From Fault Trees
• John Törnblom and Simin Nadjm-Tehrani:
  Formal Verification of Random Forests in Safety-Critical Applications
• Maryam Kamali, Sven Linker and Michael Fisher:
  Modular Verification of Vehicle Platooning with Respect to Decisions, Space and Time

12:20 - 13:30: Lunch

13:30 - 14:30: Invited talk: Cesar Munoz (chair Peter Ölveczky)

14:30 - 14:45: Break

14:45 - 15:35: Session 3: Refinement (chair: Osman Hasan)

• Nils Timm and Stefan Gruner:
  Abstraction Refinement with Path Constraints for Three-Valued Bounded Model Checking
• Karla Morris, Colin Snook, Thai Son Hoang, Rob Armstrong and Michael Butler:
  Refinement of Statecharts with Run-to-Completion Semantics

15:35 - 15:50: Coffee break

15:50 - 17:05: Session 4: Transformation and Analysis (chair: Étienne André)

• William Bombardelli Da Silva, Max Bureck, Ina Schieferdecker and Christian Hein:
  Model Transformation with Triple Graph Grammars and Non-terminal Symbols
• Yuanrui Zhang, Hengyang Wu, Yxchen Chen and Frederic Mallet:
  Embedding CCSL into Dynamic Logic: A Logical Approach for the Verification of CCSL Specifications
• Asad Ahmed, Osman Hasan and Falah Awwad:
  Formal Stability Analysis of Control Systems

17:05 - 17:15: Closing